Digital communications occur between sending and receiving devices over an intermediate communications medium, or “channel” (e.g., a fiber optic cable or insulated copper wires). Each sending device typically transmits symbols at a fixed symbol rate, while each receiving device detects a (potentially corrupted) sequence of symbols and attempts to reconstruct the transmitted data. A “symbol” is a state or significant condition of the channel that persists for a fixed period of time, called a “symbol interval.” A symbol may be, for example, an electrical voltage or current level, an optical power level, a phase value, or a particular frequency or wavelength. A change from one channel state to another is called a symbol transition. Each symbol may represent (i.e., encode) one or more binary bits of the data. Alternatively, the data may be represented by symbol transitions, or by sequences of two or more symbols.
Many digital communication links use only one bit per symbol; a binary ‘0’ is represented by one symbol (e.g., an electrical voltage or current signal within a first range), and binary ‘1’ by another symbol (e.g., an electrical voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In 4-level pulse amplitude modulation (PAM4), each symbol interval may carry any one of four symbols, typically denoted as −3, −1, +1, and +3. Each PAM4 symbol can thus represent two binary bits.
Channel non-idealities produce dispersion often causing each symbol to perturb its neighboring symbols, an effect known as inter-symbol interference (151). ISI can make it difficult for the receiving device to determine which symbols were sent in each interval, particularly when such ISI is combined with additive noise.
To combat noise and ISI, receiving devices may employ various equalization techniques. Linear equalizers generally have to balance between reducing ISI and avoiding noise amplification. Decision Feedback Equalizers (DFE) are often preferred for their ability to combat ISI without inherently requiring noise amplification. As the name suggests, a DFE employs a feedback path to remove ISI effects derived from previously-decided symbols.
A standard textbook implementation of a DFE employs a number of cascaded circuit elements to generate the feedback signal and apply it to the received input signal, all of which must complete their operation in less than one symbol interval. At a symbol interval of 100 picoseconds (for a symbol rate of 10 gigabaud), this implementation is very challenging with currently available silicon semiconductor processing technologies. Even data rates around a few gigabaud per second can be difficult to achieve due to performance limitations of silicon-based integrated circuits.
Accordingly, certain proposed designs such as those disclosed in U.S. Pat. No. 8,301,036 (“High-speed adaptive decision feedback equalizer”), U.S. Pat. No. 9,071,479 (“High-speed parallel decision feedback equalizer”), and U.S. Pat. No. 9,935,800 (“Reduced Complexity Precomputation for Decision Feedback Equalizer”), employ alternative implementations that exploit the use of precompensation modules. Each of these references is hereby incorporated herein by reference in their entireties. However, as symbol rates continue to increase, the ISI worsens, challenging even the performance of these proposed equalizers. One issue in particular is clock-signal recovery. While high-performance clock recovery modules are known, they are complex and would consume an inordinate amount of power at the sampling rates contemplated herein.